A 64 bit adder function is typically the most basic frequency limiting function in a 64 bit microprocessor. Propagating information from a carry input to the most significant bit of the adder's operand is typically the longest logical delay path in the adder. Carry look-ahead schemes have been developed to reduce the total number of logic stages in this path at the expense of added logic.
Dynamic circuit realizations have also been shown to decrease the logic delay through the adder by reducing the total gate capacitance in each logic gate by the use of precharge signals and elimination of complementary logic transistors, but at the expense of an increase in the amount of logic gates, requiring both positive true and positive complement carry signals to be generated before computation of the final sum. Greater use of digital logic for accomplishing a specific function increases the circuit area resulting in increased cost and power usage.
As is known, “positive true” logic is defined as logic which outputs a signal which is electrically at a high voltage level (e.g., VDD) when the function being evaluated by the logic is evaluated as “true” (e.g., a logical ‘1’ state). On the other hand, “positive complement” logic is defined as logic which outputs a signal which is electrically at a high voltage level (e.g., VDD) when the function being evaluated by the logic is evaluated as “complement” (e.g., a logical ‘0’ state). Of course, dynamic logic may be implemented in terms of “negative true” and “negative complement” logic. As is known, “negative true” logic is defined as logic which outputs a signal which is electrically at a low voltage level (e.g., VSS) when the function being evaluated by the logic is evaluated as “true” (e.g., a logical ‘1’ state). On the other hand, “negative complement” logic is defined as logic which outputs a signal which is electrically at a low voltage level (e.g., VSS) when the function being evaluated by the logic is evaluated as “complement” (e.g., a logical ‘0’ state). While positive or negative dynamic logic may be employed in an adder function, the descriptions herein refer to positive dynamic logic.
Thus, typical dynamic adder configurations are implemented with positive true block generate and block propagate signals, and also positive complementary versions of block generate and block propagate, to allow creating a final sum using an XOR (exclusive OR) logic circuit which is typically implemented as:S(n)=(^p(n)*C(n−1)+(p(n)*^C(n−1))  (1)p(n)=a(n)+b(n),  (2)where C(n−1) is the generate signal from bit (n−1), p(n) is the propagate signal from bit n and a(n), b(n) are two operand bits, ^ is the COMPLEMENT operator, * is the AND operator, + is the OR operator. It is to be understood that the COMPLEMENT operator ^ refers to the normal logical operation of complementing a signal, as opposed to the term “positive complementary” used with respect to dynamic circuit technology. In any case, it is known that the above representation of the final sum in equation (1) requires both a positive true and positive complementary version of C(n−1), where the positive complementary version of C(n−1) is constructed from positive complementary block generate and block propagate logic, to allow a dynamic implementation of this logic function. This stems from the requirement that dynamic logic gates require all inputs to either remain at a logic “0” state or transition only once to a logical “1” state, within a single clock cycle.